1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device that can perform a write operation 1 cycle or 2 cycles after receiving a write command without a dead cycle.
2. Description of the Prior Art
A semiconductor memory device provided with a conventional write function after 1 cycle or 2 cycles is provided with a write address during the execution of a write command. After receiving the write command and before executing the write operation, the memory device is also provided with external write data after delaying 1 or 2 cycles measured from the time of the previously provided write address.
The semiconductor memory device having such a conventional write function requires a dead cycle when changing from a read operation to a write operation and vice versa. A dead cycle requires a no operation (NOP) state that detrimentally affects bus efficiency. Accordingly, a need remains for a semiconductor memory device that can perform the write operation after 1 or 2 cycles without the need for a dead cycle.
An object of the present invention is to overcome the problems associated with prior art semiconductor memory devices.
A further object of the present invention is to provide a semiconductor memory device for executing a write function after 1 or 2 cycles without necessitating a dead cycle.
To achieve the above-described objects, a semiconductor memory device is provided. The memory device comprises address input control means for receiving an external write or read address and delaying the write address by 1 cycle when the memory device operates in a write after 1 cycle mode or by 2 cycles when the memory device operates in a write after 2 cycles mode. A data input control means receives external write data and delaying the write data by a first predetermined number of cycles when the memory device operates in the write after 1 cycle mode or delaying the write data by a second predetermined number of cycles when the memory device operates in the write after 2 cycles mode. A data transmission control means transmits the delayed write data responsive to a predetermined set of input commands. The data input control means reads the data from a cell corresponding to the read address, provides the write data to a cell corresponding to the write address using a flow through method in the write after 1 cycle mode and using a pipeline method in the write after 2 cycles mode, and writes the transmitted delayed data into the cell corresponding to the write address. The first predetermined number of cycles is either 0 or 1 and the second predetermined number of cycles are 0, 1, or 2. The data transmission control means transmits write data delayed by 0 cycles when a write, write command sequence is received in the write after 1 cycle mode, transmits write data delayed by 1 cycle when a read, write command sequence is received in the write after 1 cycle mode, transmits write data delayed by 0 cycles when a write, write, write command sequence is received in the write after 2 cycles mode, transmits write data delayed by 1 cycle when either a write, read, write or a read, write, write command sequence is received in the write after 2 cycles mode, and transmits write data delayed by 2 cycles when a read, read, write command sequence is received in the write after 2 cycles mode.